1. Field of the Invention
The present invention relates to a suitable method of driving a semiconductor display device using a display medium such as liquid crystals or EL (electro luminescence), and to a semiconductor display device using the driving method. Furthermore, the present invention relates to an electronic device using the semiconductor device display device.
2. Description of the Related Art
Techniques for manufacturing elements formed using semiconductor thin films on an insulating substrate, for example a thin film transistor (TFT), have advanced rapidly in recent years. The reason for these advancements is that the need for semiconductor display devices (typically active matrix liquid crystal display devices) has increased.
An active matrix liquid crystal display device is a device which displays an image by controlling the electric charge applied to between several hundreds of thousands and several millions of pixels, arranged in a matrix shape, by using pixel switching elements formed by transistors (pixel transistors).
Note that, throughout this specification, the term pixel refers to a structure which is mainly structured by a switching element, a pixel electrode connected to the switching element, an opposing electrode, and a passive element formed between the pixel electrode and the opposing electrode (such as a liquid crystal or electro luminescence material).
A typical example of the display operation of a liquid crystal panel of an active matrix liquid crystal display device is explained simply below using FIGS. 26A and 26B. FIG. 26A is a top surface diagram of a liquid crystal panel, and FIG. 26B is a diagram showing an arrangement of pixels.
A source signal line driver circuit 701 and source signal lines S1 to S6 are connected. Further, a gate signal line driver circuit 702 and gate signal lines G1 to G4 are connected. A plurality of pixels 703 are formed in portions surrounded by the source signal lines S1 to S6 and the gate signal lines G1 to G4. A pixel TFT 704 and a pixel electrode 705 are formed in each of the pixels 703. Note that the number of source signal lines and gate signal lines is not limited to the value shown here.
An image signal is input to the source signal line driver circuit 701 from an IC (not shown in the figures) formed external to the panel.
The image signal input to the source signal line driver circuit 701 is sampled, and is input to the source signal line S1 as a display signal. Further, the gate signal line G1 is selected in accordance with a selection signal input to the gate signal line G1 from the gate signal line driver circuit 702, and all of the pixel TFTs 704 having their gate electrode connected to the gate signal line G1 are placed in an ON state. The display signal input to the source signal line S1 is then input to the pixel electrode 705 of a pixel (1,1) through the pixel TFT 704. Liquid crystals are driven by the electric potential of the input display signal, the amount of light transmitted is controlled, and a portion of an image (image corresponding to the pixel (1,1)) is displayed.
While maintaining the state in which the image is displayed in the pixel (1,1) by using means such as a storage capacitor (not shown in the figure), the image signal input to the source signal line driver circuit 701 is sampled in the next instant, and is input to the source signal line S2 as a display signal. Note that the term storage capacitor refers to a capacitance for storing the electric potential of a display signal input to the gate electrode of the pixel TFT 704 for a fixed period.
The gate signal line G1 remains in its selected state, and the pixel TFT 704 of a pixel (1,2) of a portion at which the gate signal line G1 and the source signal line S2 intersect is placed in an on state. The display signal input to the source signal line S2 is then input to the pixel electrode 705 of the pixel (1,2) through the pixel TFT 704. Liquid crystals are driven by the electric potential of the input display signal, the amount of light transmitted is controlled, and a portion of an image (image corresponding to the pixel (1,2)) is displayed, similar to the display in the pixel (1,1).
These display operations are performed in order, and portion of the image are displayed one after another in all of the pixels (1,1), (1,2), (1,3), (1,4), (1,5), and (1,6) connected to the gate signal line G1. The gate signal line G1 continues to be selected during this period in accordance with the selection signal input to the gate signal line G1.
The gate signal line G1 becomes deselected when the display signal is input to all of the pixels connected to the gate signal line G1. Continuing, the gate signal line G2 is selected in accordance with a selection signal input to the gate signal line G2. Portions of the image are then display in order in all pixels (2,1), (2,2), (2,3), (2,4), (2,5), and (2,6) connected to the gate signal line G2. The gate signal line G2 continues to be selected during this period.
One image is displayed in a pixel portion 706 by repeating the above operations for all of the gate signal lines in order. A period during which the one image is displayed is referred to as one frame period. The period during which one image is displayed in the pixel portion 706 may also be combined with a vertical return period and taken as one frame period. The state in which the image is displayed is then maintained by means such as the storage capacitor (not shown in the figures) for all of the pixels until the pixel TFT of each pixel is again placed in an ON state.
Normally, in order to prevent degradation of the liquid crystals, the polarity of the electric potential of the signals input to each of the pixels is inverted (alternating current drive) with the electric potential of the opposing electrodes (opposing electric potential) as a reference for liquid crystal panels using TFTs as switching elements. Frame inversion drive, source line inversion drive, gate line inversion drive, and dot inversion drive can be given a method of alternating current drive. Each method is explained below.
A polarity pattern of an image signal (hereafter referred to simply as a polarity pattern) input to each pixel in frame inversion drive is shown in FIG. 27A. Note that cases in which the electric potential of the display signal input to a pixel is positive with respect to the opposing electric potential are shown by the symbol “+”, and cases in which the electric potential of the display signal input to a pixel is negative with respect to the opposing electric potential are shown by the symbol “−” in the figures displaying polarity patterns (FIGS. 27A to 27D, and FIGS. 6 to 9) within this specification. Further, the polarity pattern shown in FIGS. 27A to 27D correspond to the pixel arrangement shown in FIG. 26B.
Note that, in this specification, the term display signal having positive polarity denotes a display signal having an electric potential higher than the opposing electric potential. Further, the term display signal having a negative polarity denotes a display signal having an electric potential lower than the opposing electric potential.
In addition, there is interlaced scanning as a scanning method in which scanning is divided into two times (two fields) during one screen (one frame) by odd numbered gate signal lines and even numbered gate signal lines, and there is non-interlaced scanning in which the odd numbered and even numbered gate signal lines are not divided, with scanning performed in order. An example of using mainly non-interlaced scanning is explained here.
With frame inversion drive, display signals having the same polarity are input to all of the pixels within an arbitrary frame period (polarity pattern 1), and then the polarity of the display signals input to all of the pixels is inverted (polarity pattern 2), and display is performed. In other words, by focusing on only the polarity patterns, frame inversion drive is a method of drive in which two types of polarity patterns (the polarity pattern land the polarity pattern 2) are repeated every other frame period. Note that, in this specification, the term display signal input to a pixel denotes the display signal being input to a pixel electrode through a pixel TFT.
Source line inversion drive is explained next. A pixel polarity pattern in source line inversion drive is shown in FIG. 27B.
With source line inversion drive, display signals having the same polarity are input to all pixels connected to the same source signal line in an arbitrary frame period, and display signals having the inverse polarity are input to pixels connected to adjacent source signal lines, as shown in FIG. 27B. Note that, in this specification, the term pixels connected to a source signal line denotes pixels having a source region of a drain region of their pixel TFT connected to the source signal line.
Display signals having polarities which are the inverse of those of the arbitrary frame period are then input to each source signal line in the next frame period. Therefore, if the polarity pattern in the arbitrary frame period is taken as a polarity pattern 3, then the polarity pattern in the next frame period becomes a polarity pattern 4.
Gate line inversion drive is explained next. A pixel polarity pattern in gate line inversion drive is shown in FIG. 27C.
With gate line inversion drive, display signals having the same polarity are input to all pixels connected to the same gate signal line in an arbitrary frame period, and display signals having the inverse polarity are input to pixels connected to adjacent gate signal lines, as shown in FIG. 27C. Note that, in this specification, the term pixels connected to a gate signal line denotes pixels having the gate electrode of their pixel TFT connected to the gate signal line.
Display signals having polarities which are the inverse of those of the arbitrary frame period are then input to the pixels connected to each gate signal line in the next frame period. Therefore, if the polarity pattern in the arbitrary frame period is taken as a polarity pattern 5, then the polarity pattern in the next frame period becomes a polarity pattern 6.
In other words, gate line inversion drive is a driving method in which two types of polarity patterns (the polarity pattern 5 and the polarity pattern 6) are repeatedly displayed every other frame period, similar to source line inversion drive.
Dot inversion drive is explained next. A polarity pattern in dot inversion drive is shown in FIG. 27D.
Dot line inversion drive is a method in which the polarity of display signals input to the pixels is inverted for all adjacent pixels, as shown in FIG. 27d. Display signals in an arbitrary frame period, having polarities which are the inverse of the display signals of the preceding frame period, are input to each pixel. Therefore, if the polarity pattern in the arbitrary frame period is taken as a polarity pattern 7, then the polarity pattern in the next frame period becomes a polarity pattern 8. Namely, dot inversion drive is a driving method in which two types of polarity patterns are repeatedly displayed every other frame period.
The above alternating current drive methods are effective in preventing deterioration of liquid crystals. However, there are times when screen flicker, vertical stripes, horizontal stripes, or diagonal stripes are visible if the above alternating current drive methods are used.
It is thought that this is because, even if display of the same gray scale is performed in each pixel, display is performed when the polarity of the input display signal is positive, and when the polarity of the input display signal is negative, and there are minute differences in the screen brightness. This phenomenon is explained in detail below, using an example of frame inversion drive.
A timing chart for the active matrix liquid crystal display device shown in FIG. 26 being driven by frame inversion drive is shown in FIG. 28. Note that FIG. 28 is a timing chart for a case in which there is white display if the active matrix liquid crystal display device is normally black, and there is black display if the active matrix liquid crystal display device is normally white. A period during which a selection signal is input to one gate signal line is taken as one line period, and a period in which selections signals are input to all of the gate signal lines and one image is displayed is taken as one frame period.
When a display signal is input to the source signal line S1 and a selection signal is input to the gate signal line G1, a positive polarity display signal is input to the pixel (1,1) formed in the portion at which the source signal line S1 and the gate signal line G2 intersect. The electric potential imparted to the pixel electrode in the pixel (1,1) in accordance with the input display signal then ideally continues to be stored throughout the frame period in accordance with means such as a storage capacitor.
However, in practice, when the electric potential of the gate signal line G1 shifts to an electric potential for placing the pixel TFT in an OFF state when the one line period is complete, the electric potential of the pixel electrode is dragged by ΔV in the direction of the shift in the gate signal line G1 electric potential. This phenomenon is referred to as field through, and the voltage DV is referred to as a punch through voltage.
The punch through voltage ΔV is expressed by the following equation.ΔV=V×Cgd/(Cgd+Clc+Cs)
In the above equation, V is the amplitude of the gate electrode electric potential, Cgd is the capacitance between the gate electrode and the drain region of the pixel TFT, Clc is the capacitance of the liquid crystals between the pixel electrode and the opposing electrode, and Cs is the capacitance of the storage capacitor.
In the timing chart shown in FIG. 28, the actual electric potential of the pixel electrode in the pixel (1,1) is shown by a solid line, and the ideal electric potential of a pixel electrode in which field through is not considered is shown by a dotted line. In a first frame period, a positive polarity display signal is input to the pixel (1,1). The electric potential of the gate signal line changes in the negative direction at the same time as the first line period is completed in the first frame period shown in FIG. 28, and the electric potential of the pixel electrode of the pixel (1,1) also actually changes in the negative direction by the amount of the punch through voltage. Note that, in FIG. 28, the punch through voltage during in the first frame period is denoted by the symbol ΔV1.
Next, in a first line period of a second frame period, a negative polarity display signal, having a polarity which is the inverse of that of the first line period of the first frame period, is input to the pixel (1,1). The electric potential of the gate signal line G1 then changes in the negative direction when the first line period is completed in the second frame period. The electric potential of the pixel electrode of the pixel (1,1) also actually changes, at the same time, in the negative direction by the amount of the punch through voltage. Note that, in FIG. 28, the punch through voltage during in the second frame period is denoted by the symbol ΔV2.
The drive voltage after the first line period of the first frame period is complete is shown by the reference symbol V1, and the drive voltage after the first line period of the second frame period is complete is shown by the reference symbol V2 in FIG. 28. Note that the term drive voltage denotes the electric potential difference between the electric potential of the pixel electrode and the electric potential of the opposing electrode in this specification.
The drive voltage V1 and the drive voltage V2 have a voltage difference of ΔV1+ΔV2. The brightness of the image in the pixel (1,1) therefore differs in the first frame period and the second frame period.
A method in which the value of the opposing electric potential is made lower can also be considered so as to make the values of the drive voltage V1 and the drive voltage V2 become the same.
However, the capacitance Cgd between the gate electrode and the drain region of the pixel TFT has different values when positive polarity and negative polarity display signals are input to the pixel. In addition, the capacitance Clc of the liquid crystal between the pixel electrode and the opposing electrode also changes in accordance with the electric potential of the display signal input to the pixel. The value of the punch through voltage ΔV therefore also changed with each frame period because of differing values of Cgd and Clc in each frame period. Consequently, even if the value of the opposing electric potential is changed, for example, the drive voltage in the pixel (1,1) changed in accordance with the frame period, and the resulting image brightness changes.
This is a phenomenon not limited to the pixel (1,1), and occurs in all of the pixels. The brightness of the pixels therefore differs due to the polarity of the display signals input to the pixels.
The brightness of the image displayed in the first frame period differs from that of the image displayed in the second frame period in frame inversion drive, and this is seen as flicker by an observer. In particular, conspicuous flicker is confirmed in the display of intermediate gray scales.
The brightness of the display also similarly differs in source line inversion drive, gate line inversion drive, and dot inversion drive between pixels to which a positive polarity display signal is input and pixels to which a negative polarity display signal is input.
Consequently, vertical stripes are displayed on the screen with source line inversion drive, and horizontal stripes are displayed with gate line inversion drive. Furthermore, there are times at which vertical stripes, horizontal stripes, or diagonal stripes appear with dot inversion drive, depending upon the image displayed in the screen.
It has been considered that increasing the frame frequency would be effective in order to prevent flicker from being able to be seen on the screen, and in order to prevent vertical stripes, horizontal stripes, and vertical stripes from being visible with alternating current drive.
However, it is necessary to increase the frequency of the image signal input to the IC in order to increase the frame frequency. If the frequency of the image signal is raised, it then becomes necessary to increase the specification of electronic devices for generating the image signal, and the cost is increased. Further, the drive frequency of the electronic devices that generate the image signal becomes unable to handle the image signal frequency, and a load is imparted on the electronic devices that generate the image signals. Operation may become impossible, and there is the possibility that difficulties will develop due to reliability.